1. Field of the Invention
This invention relates to a chopper-type voltage comparison apparatus.
2. Description of the Prior Art
FIG. 1 is a circuit diagram showing, by way of example, the arrangement of a conventional chopper-type voltage comparison apparatus as disclosed in Japanese Patent Application Laid-Open No. 61-33011(1986).
The voltage comparison apparatus consists essentially of an input unit 1 and an amplifier unit 100 having two stages of amplifier circuits 2 and 3.
The input unit 1 comprises a first switch S1 connected at one end to a first input terminal 4 and at the other end to an output terminal 6 and adapted to be ON/OFF controlled by a clock .phi..sub.1, and a second switch S2 connected at one end to a second input terminal 5 and at the other end to aforesaid output terminal 6 and adapted to be ON/OFF controlled by a clock .phi..sub.2 which acts in complementary relation with the clock .phi..sub.1.
A first voltage V.sub.1 to be compared is applied to the first input terminal 4, and a second voltage V.sub.2 to be compared is applied to the second input terminal 5.
The amplifier circuit 2, for which the output terminal 6 of the input unit 1 serves as an input terminal, includes a coupling capacitor C.sub.1 connected at one end to the input terminal, an inverting amplifier 11 having its input connected through a node 7 to the other end of the capacitor C.sub.1 and having its output connected to an output terminal 8, and a feedback route switch S3 connected at one end to the node 7 and at the other end to the output terminal 8 and adapted to be ON/OFF controlled by the clock .phi..sub.1.
The amplifier circuit 3, for which the output terminal 8 of the amplifier circuit 2 serves as an input terminal, includes a coupling capacitor C.sub.2 connected at one end to the input terminal, an inverting amplifier 12 having its input connected through a node 9 to the other end of the coupling capacitor C.sub.2 and having its output connected to an output terminal 10, and a feedback route switch S4 connected at one end to the node 9 and at the other end to the output terminal 10 and adapted to be ON/OFF controlled by the clock .phi..sub.2.
Operation of such conventional voltage comparison apparatus will be explained with reference to a timing chart shown in FIG. 2.
In FIG. 2, characters (a), (b), (c), (d), (e), (f) and (g) designates, respectively, clock .phi..sub.1 ; clock .phi..sub.2 ; potential V.sub.6 at output terminal 6 of the input unit 1; potential V.sub.7 at node 7 of the amplifier circuit 2; potential V.sub.8 at output terminal 8 of the amplifier circuit 2; potential V.sub.9 at node 9 of the amplifier circuit 3; and potential V.sub.10 at output terminal 10 of the amplifier circuit 3.
As FIG. 2 (a) shows, when clock .phi..sub.1 is at "1" (at high level), the first switch S1 and feedback route switch S3 turn on and the second switch S2 turns off. Thus, the node 7 of the amplifier circuit 2 and the output terminal 8 are short-circuited relative to each other. Such operating condition of the amplifier circuit is hereinafter referred to as "auto zero mode".
In the condition of auto zero mode, there is potential equality between the node 7 and the output terminal 8 in the amplifier circuit 2. Therefore, the potential between the node 7 and the output terminal 8 in the amplifier circuit 2 in such case is equal to a potential Vbal determined by an intersecting point M in a transfer characteristic curve m of the inverting amplifier 11 (12) relative to a straight line 1 satisfying the relation "output voltage"="input voltage" as shown in FIG. 3 (the potential Vbal is hereinafter referred to as balance potential). Accordingly, in a period of this mode, the coupling capacitor C.sub.1 is charged by input voltage V.sub.1 applied through the first switch S1 and also by balance voltage Vbal 1 of the inverting amplifier 11.
While clock .phi..sub.1 is at "0" (at low level), the first switch S1 and the feedback route switch S3 turn off and, on the other hand, the second switch S2 turns on. Such condition of operation of the amplifier circuit is hereinafter referred to as "comparison mode".
In the condition of comparison mode, by turning off of the feedback route switch S3, the input side impedance of the inverting amplifier 11 becomes infinite. Accordingly, any voltage variation "V.sub.2 -V.sub.1 " (hereinafter referred to as input differential voltage) occurring at the input side of the coupling capacitor C.sub.1 is transmitted to the output-side node 7 of the coupling capacitor C.sub.1, and is inversely amplified at the inverting amplifier 11. As FIG. 2 (e) shows, a final voltage at the output terminal 8 in a period of comparison mode operation is V.sub.8, the voltage variation at the output terminal 8 is expressed as "V.sub.8 -Vbal 1".
Operation of the amplifier circuit 3 is performed as follows.
When clock .phi..sub.1 is at "0", or clock .phi..sub.2 in FIG. 2 (b) is at "1", the feedback route switch S4 turns on and the amplifier circuit 3 goes into auto zero mode. In this case, the amplifier circuit 2 becomes in comparison mode; therefore, in a period of such operation mode, the coupling capacitor C.sub.2 is charged by output voltage V.sub.8 of the amplifier circuit 2 in comparison mode and also by balance voltage Vbal 2 of the inverting amplifier 12.
As clock .phi..sub.1 again goes into "1", that is, clock .phi..sub.2 goes into "0", the feedback route switch S4 turns off and the amplifier circuit 3 goes into comparison mode. In this case, the amplifier circuit 2 takes auto zero mode, and accordingly the potential of the output terminal 8 changes from V.sub.8 to balance voltage Vbal 1.
Meanwhile, the amplifier circuit 3 which is then in comparison mode detects a voltage variation ".DELTA.V.sub.8 =Vbal 1-V.sub.8 " occurring at its input terminal 9 and same is inversely amplified. If a final voltage at the output terminal 10 in the period is V.sub.10 as FIG. 2 (g) shows, the output voltage variation at the output terminal 10 is "V.sub.10 -Vbal 2".
With such conventional voltage comparison apparatus in which the amplifier circuit is of the two stage arrangement, it is very unlikely to obtain sufficient voltage gains. In practice, therefore, a further amplifier circuit or inverting amplifier is connected to the apparatus in order to provide desired voltage gains. In the conventional voltage comparison apparatus of such arrangement, voltages V.sub.1 and V.sub.2 applied respectively on the first input terminal 4 and the second input terminal 5 are compared to determine their difference in potential and finally digital signal "1" (high level) or "0" (low level) are issued.
Now, such conventional voltage comparison apparatus of the chopper type as above described, in which the amplifier circuits 2 and 3 are operated by complementary clocks, has only a small margin of operational flexibility relative to the effect of input voltage difference variable clock by clock and/or relative to delicate time lags between clocks, which may lead to malfunctions or may involve the possibility of no sufficient voltage gain being obtained. This point will be discussed in detail below.
First, possible malfunctions or drop in voltage gains due to input voltage variations will be explained.
FIG. 4 is a timing chart showing conditions of operation of the conventional chopper type voltage comparison apparatus in the case where rising duration of clock and falling duration of clock are taken into consideration. There are shown voltage variations occurring especially when the amplifier circuit 2 changes from auto zero mode to comparison mode and when the amplifier circuit 3 changes from comparison mode to auto zero mode.
In FIG. 4, (a) and (b) show clock timing patterns for clock .phi..sub.1 and clock .phi..sub.2 respectively; and (e), (f), (g) show voltage wave forms at output terminal 8, node 9, and output terminal 10 respectively. Feedback route switches S3 and S4 are both comprised of transmission gates; and Va1, Vb1 represent voltage wave forms applied to N channel type MOS transistor gates, and Va2, Vb2 represent voltage wave forms applied to P channel type MOS transistor gates.
Therefore, Va1 and Vb2 correspond to clock .phi..sub.1 and Va2 and Vb1 correspond to clock .phi..sub.2.
It is noted that in FIG. 4, Vdd and Vss represent a high voltage source and a low voltage source respectively.
As earlier stated, the amplifier circuit 2 goes in auto zero mode when clock .phi..sub.1 is "1", and it goes in comparison mode when clock .phi..sub.1 is "0". Both input voltage and output voltage of the inverting amplifier 11 in auto zero mode are a balance voltage Vbal 1 (usually set at a medium value between Vdd and Vss), therefore a transition point between the two modes is a potential at which voltage between gate and source is smaller than a threshold limit voltage, namely, EQU (Va1-Vbal1)=Vtn1
or a potential at which the following relation is satisfied; EQU (Vbal1-Va2)=.vertline.Vtp1.vertline..
In the above relations, Vtn1 and .vertline.Vtp1.vertline. represent threshold limit voltages for N channel type MOS transistor and P channel type MOS transistor respectively. Therefore, assuming that the both are equal in value, the transition point between the two modes is at the time when t=t1 as shown in FIG. 4.
In the amplifier circuit 3, mode becomes comparison mode when clock .phi..sub.1 is "1" (high level), or in other words, when clock .phi..sub.2 is "0" (low level), and again mode becomes comparison mode when clock .phi..sub.1 is "0", or in other words when clock .phi..sub.2 is "1". Therefore, the output amplitude of the amplifier circuit 3 in comparison mode is comparatively small. Thus, assuming that the voltage level of the circuit is generally equal to balance voltage Vbal 2 (for example, if input voltage difference is 1 mV, and voltage gain per stage of amplifier circuit is 10, the output amplitude of the amplifier circuit 3 is 0.1 V), the point of transition from comparison mode to auto zero mode in the amplifier circuit 3, as is the case with the amplifier circuit 2, is at the time when t=t2 as FIG. 4 shows.
Therefore, in such case, the amplifier circuit 2 and the amplifier circuit 3 are not in fully complementary relation to each other in operation, there being periods in which both circuits are in comparison mode, that is, periods which meet the relation t1.ltoreq.t.ltoreq.t2. This may be a cause of malfunction.
It is believed that such malfunction can occur, for example, when there is a minor input voltage difference during a preceding clock cycle and when there is a large input voltage difference during a next following clock cycle. Such situation is illustrated in cases (e), (f) and (g) of FIG. 4.
When a large input voltage difference is applied, as FIG. 4 (e) shows, the output voltage of the amplifier circuit 2 abruptly fluctuates at a wide amplitude in a region of t.gtoreq.t1. On the other hand, the input of the amplifier circuit 3, when t.ltoreq.t1, is stable at a certain voltage with a minor amplitude under the influence of total input, and when t1.ltoreq.t.ltoreq.t2, as FIG. 4 (f) shows, a voltage variation at the output terminal 8 of the amplifier circuit 2 is transmitted to the amplifier circuit 3 because comparison mode is present, and as a result there arises a voltage variation in the amplifier 3.
If such voltage variation is of same polarity as a voltage variation occurred previously to the period of t=t1, there is no particular problem, but if the change is different in polarity, there arises a problem. That is, when the variation in voltage is different in polarity, the amplitude of the voltage relative to balance voltage Vbal 2 of the amplifier circuit 3 is small. In other words, available voltage gain is small, or there is a possibility of malfunction.
The foregoing description relates to the case where a large input voltage difference occurs after one clock cycle in which a minor input voltage difference is present; but even in the case where only a small input voltage difference is involved, there is a possibility of malfunction or voltage gain drop.
When there is a somewhat large input voltage difference the amplitude of outputs at the output terminal 10 of the amplifier circuit 3 is comparatively large. In such a case, therefore, voltage between gate and source of either the N channel type MOS transistor or the P channel type MOS transistor is large, and accordingly the timing for turn on of the transmission gate is quickened and time lag between t1 and t2 is reduced. The magnitude of the possibility of malfunction and possible drops in voltage gain depend on the degree of variation in input voltage difference which may vary clock after clock. Malfunctions and voltage gain drops will occur under composite infuence of those factors.
In the above described instance, it is assumed that the feedback route switches S3, S4 are comprised of transmission gates. In the case where the switches are comprised of N-channel type or P-channel type transistors, it is likely that, depending upon the polarity of output amplitude, there will be greater time lag between t1 and t2, and accordingly there may be a more serious problem.
The above described problem concerns the case where emphasis is put on input voltage difference and rising duration and falling duration. But in the case where there is a time lag between clock .phi..sub.1 and clock .phi..sub.2, a similar problem will occur. This point will be explained with reference to FIGS. 5 and 6.
FIG. 5 is a timing chart illustrating the case where there is a time lag of td between the timing for transition of clock .phi..sub.1 from "1" to "0" and the timing for transition of clock .phi..sub.2 from "0" to "1".
In FIG. 5, (a) and (b) show clock timings for clock .phi..sub.1 and clock .phi..sub.2 respectively, and (e), (f) and (g) show voltage wave forms at the output terminal 8, the node 9, and the output terminal 10 respectively.
The amplifier circuit 2 goes into comparison mode when t.ltoreq.t1, and into auto zero mode when t.gtoreq.t1. The amplifier circuit 3 goes into auto zero mode when t.ltoreq.t2, and into comparison mode when t.gtoreq.t2. Accordingly, there are periods in which the two amplifier circuits 2 and 3 are simultaneously in auto zero mode, that is, t1.ltoreq.t.ltoreq.t2, which is a cause of voltage gain drop. This point is specifically explained below.
In FIG. 2, the output of the amplifier circuit 2, that is, voltage variation .DELTA.V8 at the output terminal 8 in the course of transition from comparison mode to auto zero mode is transmitted to the input side node 9 of the amplifier circuit 3, and the same is further amplified by the inverting amplifier 12, which is as already mentioned. If there is a period in which both the amplifier circuits 2 and 3 simultaneously become auto zero mode, the amplitude of voltage variation at the output terminal 8 of the amplifier circuit 2 is considerably lowered when it is transferred to the later stage.
As FIG. 6 shows, the voltage at the output terminal 8 when t=t1 is V8, and the voltage when t=t2 is V8'. In this case, since the amplifier circuit 3 is in auto zero mode, voltage variations "V8-V8'" during the period of "t=t1-t2" are not transmitted to the amplifier circuit 3; accordingly, voltage variations actually detected are those which have occurred after t=t2, that is "V8'-Vbal 2". If the voltage variation is taken as .DELTA.V8', then the amplitude of outputs of the amplifier circuit 3 corresponds to a value obtained by multiplying the voltage variation amplification factor, and if the amplification factor is same, the resulting amplitude is considerably smaller than the case where value .DELTA.V8 is applied. By this reason, there will be a voltage gain drop due to the time lag between clock .phi..sub.1 and clock .phi..sub.2.